mce: k7 cleanup

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>

diff --git a/xen/arch/x86/cpu/mcheck/k7.c b/xen/arch/x86/cpu/mcheck/k7.c
index 7b5ea16dc9a3695c8b1c6c17080be6cead19ae55..ec984f8e91202db4c21cf3a0d8cb2810ad6a3d23 100644 (file)
--- a/xen/arch/x86/cpu/mcheck/k7.c
+++ b/xen/arch/x86/cpu/mcheck/k7.c
@@ -19,51 +19,53 @@
 /* Machine Check Handler For AMD Athlon/Duron */
 static fastcall void k7_machine_check(struct cpu_user_regs * regs, long error_code)
 {
-       int recover=1;
-       u32 alow, ahigh, high, low;
-       u32 mcgstl, mcgsth;
+       int recover = 1;
+       uint64_t msr_content, mcgst;
        int i;
 
-       rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
-       if (mcgstl & (1<<0))    /* Recoverable ? */
-               recover=0;
+       rdmsrl(MSR_IA32_MCG_STATUS, mcgst);
+       if (mcgst & MCG_STATUS_RIPV)    /* Recoverable ? */
+               recover = 0;
 
-       printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
-               smp_processor_id(), mcgsth, mcgstl);
+       printk(KERN_EMERG "CPU %d: Machine Check Exception: 0x%016"PRIx64"\n",
+               smp_processor_id(), mcgst);
 
-       for (i=1; i<nr_mce_banks; i++) {
-               rdmsr (MSR_IA32_MCx_STATUS(i),low, high);
-               if (high&(1<<31)) {
-                       if (high & (1<<29))
+       for (i = 1; i < nr_mce_banks; i++) {
+               uint64_t value;
+
+               rdmsrl(MSR_IA32_MCx_STATUS(i), msr_content);
+               if (msr_content & MCi_STATUS_VAL) {
+                       if (msr_content & MCi_STATUS_UC)
                                recover |= 1;
-                       if (high & (1<<25))
+                       if (msr_content & MCi_STATUS_PCC)
                                recover |= 2;
-                       printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
-                       high &= ~(1<<31);
-                       if (high & (1<<27)) {
-                               rdmsr (MSR_IA32_MCx_MISC(i), alow, ahigh);
-                               printk ("[%08x%08x]", ahigh, alow);
+                       printk(KERN_EMERG "Bank %d: 0x%16"PRIx64,
+                               i, msr_content);
+                       msr_content &= ~MCi_STATUS_VAL;
+                       if (msr_content & MCi_STATUS_MISCV) {
+                               rdmsrl(MSR_IA32_MCx_MISC(i), value);
+                               printk("[0x%016"PRIx64"]", value);
                        }
-                       if (high & (1<<26)) {
-                               rdmsr (MSR_IA32_MCx_ADDR(i), alow, ahigh);
-                               printk (" at %08x%08x", ahigh, alow);
+                       if (msr_content & MCi_STATUS_ADDRV) {
+                               rdmsrl(MSR_IA32_MCx_ADDR(i), value);
+                               printk(" at 0x%016"PRIx64, value);
                        }
-                       printk ("\n");
+                       printk("\n");
                        /* Clear it */
-                       wrmsr (MSR_IA32_MCx_STATUS(i), 0UL, 0UL);
+                       wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
                        /* Serialize */
                        wmb();
                        add_taint(TAINT_MACHINE_CHECK);
                }
        }
 
-       if (recover&2)
-               mc_panic ("CPU context corrupt");
-       if (recover&1)
-               mc_panic ("Unable to continue");
-       printk (KERN_EMERG "Attempting to continue.\n");
-       mcgstl &= ~(1<<2);
-       wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+       if (recover & 2)
+               mc_panic("CPU context corrupt");
+       if (recover & 1)
+               mc_panic("Unable to continue");
+       printk(KERN_EMERG "Attempting to continue.\n");
+       mcgst &= ~MCG_STATUS_MCIP;
+       wrmsrl(MSR_IA32_MCG_STATUS, mcgst);
 }
 
 
@@ -76,10 +78,10 @@ enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c)
 
        /* Clear status for MC index 0 separately, we don't touch CTL,
         * as some Athlons cause spurious MCEs when its enabled. */
-       wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
-       for (i=1; i<nr_mce_banks; i++) {
-               wrmsr (MSR_IA32_MCx_CTL(i), 0xffffffff, 0xffffffff);
-               wrmsr (MSR_IA32_MCx_STATUS(i), 0x0, 0x0);
+       wrmsrl(MSR_IA32_MC0_STATUS, 0x0ULL);
+       for (i = 1; i < nr_mce_banks; i++) {
+               wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL);
+               wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
        }
 
        return mcheck_amd_k7;